As a result of improvements in the integration of semiconductor devices, including the development of manufacturing and design techniques, attempts have been made to construct systems using a single chip (i.e. one chip). Technique relating to one-chip systems have developed focusing on techniques for integrating a controller and circuits which operate with a low voltage on a single chip.
However, to reduce the weight and size of systems, it may be necessary to form a circuit unit that controls the power supply of the system. For example, input and output ports and a main circuit may be formed in a single chip. Since an input port and an output port may include circuits including high-voltage power transistors which receive a relatively high voltage, the input port and the output port may not rely solely on general low-voltage CMOS circuits.
Accordingly, in order to minimize the size and/or weight of a system, the input and output ports of a power supply and a controller may need to be formed in a single chip. A power IC technique may be implemented in which a high-voltage transistor and a low-voltage CMOS transistor circuit are formed in a single chip. A power IC technique may improve the structure of a VDMOS (Vertical DMOS) device, which is a discrete power transistor of the related art. A lateral DMOS (LDMOS) may be implemented in which a drain is arranged laterally to allow a current to flow laterally and a drift region may be arranged between the channel and the drain to secure high-voltage breakdown.
Aspects of a LDMOS device of the related art are described with reference to FIG. 1. FIG. 1 is a cross sectional view illustrating the structure of an LDMOS device in accordance with the related art. NBL (N-Buried Layer) 90 and HV NWELL (High Voltage N-WELL) 80 may be formed in semiconductor substrate P-SUB with an active region defined by field oxide film 60. HV NWELL (High Voltage N-WELL) 80 may be formed on. NBL 90.
Gate pattern 50 may be formed on/over the semiconductor substrate to overlap field oxide film 60. P-body 30 may be formed in HV NWELL (High Voltage N-WELL) 80 on one side of gate pattern 50. Source region 40 may be formed in P-body 30. LV NWELL (Low Voltage N-WELL) 70 may be formed in HV NWELL (High Voltage N-WELL) 80 on the other side of gate pattern 50. Drain region 10 may be formed in LV NWELL 70.
A related art LDMOS device may have a structure in which deep sink region (DEEPN+) 20 separated from drain region 10 by field oxide film 60 is used as a guard ring, thereby preventing or minimizing parasitic PNP operation. For example, if deep sink region 20 is used as a guard ring, when current flows backward in an inductor (i.e. when a hole current is generated), holes may recombine in NBL 90 and un-recombined holes may flow into deep sink region 20 to prevent the hole current from flowing into the substrate, thereby preventing or minimizing parasitic PNP operation.
In the related art, deep sink region 20 may be used as a guard ring in an LDMOS device of the related art and deep sink region 20 may be formed by a diffusion process using POCl3 (phosphorus oxychloride) or an ion implantation process. However, in the related art, a diffusion process using POCl3 (phosphorus oxychloride) or an ion implantation process or similar process may have a relatively long process time, which may contribute to relatively high costs.